Electron Mobility Transistor Direct-Coupled FET Logic Inverters

The monolithic integration of enhancementand depletion-mode (Eand D-mode) high electron mobility transistors (HEMTs) lattice-matched to InP is of interest in the area of circuits for low power, high speed communications. When compared to circuits implemented in depletion-mode @-mode) only technology, circuits implemented in ED-mode technology enjoy a number of advantages. D-mode only circuits require level-shifting between successive cascaded stages, where ED-mode circuits do not. The extra level-shifting circuitry increases power consumption and chip area, as well as circuit design and layout complexity (1). In addition, E/D-mode circuits can operate on a single power supply, whereas such operation of D-mode only circuits can be achieved only through increased circuit complexity. There has been some modest success in the development of an integrated ED technology on lattice-matched InP (2). Recently, a process for the fabrication of high speed E-mode HEMTs on lattice-matched InP has been reported (5), as well as for the monolithic integration of Eand D-mode devices on a common substrate (6).